New Options

This topic lists the options or option settings that provide new functionality in this release.

If no label appears, the option is available on all supported systems.

If "only" appears in the label, the option is only available on the identified system.

For more details on the options, refer to the individual option descriptions.

For information on conventions used in this table, see Notational Conventions.

New compiler options or option settings are listed in tables below:

Windows* Options

Description

Default

/Qauto-arch

Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for x86 architecture processors if there is a performance benefit.

OFF

/Qconditional-branch=keyword

Lets you identify and fix code that may be vulnerable to speculative execution side-channel attacks, which can leak your secure data as a result of bad speculation of a conditional branch direction.

/Qconditional-branch:keep

/Qopt-multiple-gather-scatter-by-shuffles[-]

Enables or disables the optimization for multiple adjacent gather/scatter type vector memory references.

varies; see the option description

/Qpar-loops

Lets you select between old or new implementations of parallel loop support.

/Qpar-loops:new

Linux* and macOS* Options

Description

Default

-mauto-arch

Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for x86 architecture processors if there is a performance benefit.

OFF

-mconditional-branch=keyword

Lets you identify and fix code that may be vulnerable to speculative execution side-channel attacks, which can leak your secure data as a result of bad speculation of a conditional branch direction.

-mconditional-branch=keep

-par-loops

Lets you select between old or new implementations of parallel loop support.

-par-loops=new

-q[no-]opt-multiple-gather-scatter-by-shuffles

Enables or disables the optimization for multiple adjacent gather/scatter type vector memory references.

varies; see the option description

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804