Offload Compilation, OpenMP*, and Parallel Processing Options
This section contains descriptions for compiler options that pertain to offload compilation, OpenMP*, or parallel processing. They are listed in alphabetical order.
device-math-lib
Enables or disables certain device libraries. This is a deprecated option that may be removed in a future release.
fintelfpga
Lets you perform ahead-of-time (AOT) compilation for the Field Programmable Gate Array (FPGA).
fiopenmp, Qiopenmp
Enables recognition of OpenMP* features, such as parallel, simd, and offloading directives. This is an alternate option for compiler option [Q or q]openmp.
flink-huge-device-code
Tells the compiler to place device code later in the linked binary. This is to prevent 32-bit PC-relative relocations between surrounding Executable and Linkable Format (ELF) sections when the device code is larger than 2GB.
fno-sycl-libspirv
Disables the check for libspirv (the SPIR-V* tools library).
foffload-static-lib
Tells the compiler to link with a fat (multi-architecture) static library. This is a deprecated option that may be removed in a future release.
fopenmp
Option -fopenmp is a deprecated option that will be removed in a future release.
fopenmp-target-buffers, Qopenmp-target-buffers
Enables a way to overcome the problem where some OpenMP* offload SPIR-V* devices produce incorrect code when a target object is larger than 4GB.
fsycl
Enables a program to be compiled as a SYCL program rather than as plain C++11 program.
fsycl-add-targets
Lets you add arbitrary device binary images to the fat SYCL* binary when linking. This is a deprecated option that may be removed in a future release.
fsycl-enable-function-pointers
Enables function pointers and support for virtual functions for SYCL kernels and device functions. This is an experimental feature.
fsycl-esimd-force-stateless-mem
Determines whether the compiler enforces stateless memory accesses within ESIMD kernels on the target device. This is an experimental feature.
fsycl-explicit-simd
Enables or disables the experimental "Explicit SIMD" SYCL* extension. This is a deprecated option that may be removed in a future release.
fsycl-force-target
Forces the compiler to use the specified target triple device when extracting device code from any given objects on the command line.
fsycl-help
Causes help information to be emitted from the device compiler backend.
fsycl-host-compiler
Tells the compiler to use the specified compiler for the host compilation of the overall offloading compilation that is performed.
fsycl-instrument-device-code
Enables or disables linking of the Instrumentation and Tracing Technology (ITT) device libraries for VTune™.
fsycl-link
Tells the compiler to perform a partial link of device binaries to be used with Field Programmable Gate Array (FPGA).
fsycl-link-huge-device-code
Tells the compiler to place device code later in the linked binary. This is to prevent 32-bit PC-relative relocations between surrounding Executable and Linkable Format (ELF) sections when the device code is larger than 2GB. This is a deprecated option that will be removed in a future release.
fsycl-link-targets
Tells the compiler to link only device code. This is a deprecated option that may be removed in a future release.
fsycl-max-parallel-link-jobs
Tells the compiler that it can simultaneously spawn up to the specified number of processes to perform actions required to link SYCL applications. This is an experimental feature.
fsycl-optimize-non-user-code
Tells the compiler to optimize SYCL framework utility functions and to leave the kernel code unoptimized for further debugging.
fsycl-pstl-offload
Enables the offloading of C++ standard parallel algorithms to a SYCL device. This is an experimental feature.
fsycl-rdc
Determines whether the compiler generates device code in one module (normal behavior) or it generates separate device code per source.
fsycl-targets
Tells the compiler to generate code for specified device targets.
fsycl-use-bitcode
Tells the compiler to produce device code in LLVM Intermediate Representation (IR) bitcode format into fat objects.
ftarget-compile-fast
Tells the compiler to perform less aggressive optimizations to reduce compilation time at the expense of generating less optimal target code. This is an experimental feature.
ftarget-export-symbols
Exposes exported symbols in a generated target library to allow for visibility to other modules.
nolibsycl
Disables linking of the SYCL* runtime library.
qopenmp, Qopenmp
Enables recognition of OpenMP* features and tells the parallelizer to generate multi-threaded code based on OpenMP* directives.
qopenmp-link
Controls whether the compiler links to static or dynamic OpenMP* runtime libraries.
reuse-exe
Tells the compiler to speed up Field Programmable Gate Array (FPGA) target compile time by reusing a previously compiled FPGA hardware image.
Wno-sycl-strict
Disables warnings that enforce strict SYCL* language compatibility.
Xopenmp-target
Enables options to be passed to the specified tool in the device compilation tool chain for the target.